Simulation of SOI MOSFET using ATLAS

Silicon on insulator (SOI) CMOS offers performance gain over bulk CMOS mainly due to reduced parasitic capacitances and latchup. It is most promising technology when low cost low power and low voltage suppply is required. kink effect and self heating are two important points of concern in case of SOI MOSFET. In this paper we first briefly discuss the SOI technology, kink effect and lattice heating in SOI MOSFET's and then we present the simulation results obtained using the industry standard software ATLAS from SILVACO. Keywords-Silicon on insulator, SOI MOSFET, Kink effect, ATLAS, Lattice heating Introduction Silicon is the most commonly used material in contemporary IC technology. In a modern day IC there may be millions of transistors on a small piece of silicon. Naturally the fabrication and design of these IC’s cannot be done without computer aids. Both the fabrication and design of these IC’s require Electronic Design Automation tools(EDA). There is a need for highly precise software tools to analyze and simulate the design and fabrication of integrated circuits. Lot of research has been done and still going on these issues. As a result we have got highly useful tools for design and fabrication of IC’s. CMOS technology has been the driving technology for whole microelectronics industry for last many years. But the major problem associated with cmos is the parasitic capacitances which becomes prohibitively large as we goto lesser channel lengths. So people have proposed various ideas to counter this problem. One of the solution is Silicon On Insulator(SOI) technology. In silicon on insulator technology small islands of silicon are formed on an insulator film. Circuits are fabricated on these islands of silicon. Using SOI fabrication process coupled with lateral isolation techniques we can get circuits with very small parasitic capacitances and latchup free circuits. Silicon on insulator technology CMOS integrated circuits are almost exclusively fabricated on bulk silicon substrates for two well known reasons: the availability of electronicgrade material and because a good quality oxide can be readily grown on silicon, a process which is not possible on germanium or on compound semiconductors. Yet modern MOSFET’s made in silicon are far from the ideal structure. Bulk MOSFET’s are made in silicon wafers having a thickness of approximately 800micrometers but only the first micrometer at the top of the wafer are used for transistor fabrication. Interactions between the devices and the substrate give rise to a range of unwanted parasitic effects. One of these parasitic is the capacitance between diffused source and drain and substrate. This capacitance increases with substrate doping and becomes larger in modern submicron devices where the doping concentration in the substrate is higher than in previous MOS technologies. In addition latchup which consist of the unwanted thyristor inherently present in all bulk CMOS structures becomes a serious problem in devices with small dimensions. The solution is SOI MOSFET. The SOI MOSFET contains the traditional three terminals (source, drain and gate which controls a channel in which current flows from source to drain). However the full dielectric isolation of devices prevents the occurrence of most of the parasitic effects experienced in bulk silicon devices. Most parasitic effects in bulk MOS devices find their origin in the interactions between the device and the substrate. Latch up in bulk devices finds its origin in the PNPN structure of the CMOS inverter. The latchup can be symbolized by two bipolar transistors formed by the substate, the well and the source and drain junctions. For latchup to occur the current gain of the loop formed by the two transistors should be greater than one. In an SOI CMOS inverter the silicon film containing the active devices is thin enough for the junction to reach through to the buried insulator. A latchup path is ruled out because there is no current path to the substrate. In addition the lateral PNPN structures contain heavily doped bases that virtually reduce the gain of the bipolar devices to zero.